📋 FIFO UVM Testbench

A comprehensive Universal Verification Methodology testbench for FIFO design verification

UVM SystemVerilog Verification FPGA

Project Overview

The FIFO UVM Testbench is a complete, production-ready verification environment for testing FIFO (First-In-First-Out) designs using the Universal Verification Methodology. This project demonstrates best practices in UVM testbench design with comprehensive stimulus generation, coverage collection, and verification.

The testbench supports parameterized data width (8 bits) and depth (16 elements) FIFO with full handshake protocol including write acknowledge and read valid signals. It includes directed tests, random stimulus generation, reference model verification, and an advanced FIFO Tracker component for real-time operation monitoring.

FIFO Specifications

8

Data Width (bits)

16

Depth (Elements)

11

UVM Components

3

Test Scenarios

✨ Key Features

🎯 Complete UVM Environment

Fully functional testbench with agent, driver, monitor, sequencer, scoreboard, reference model, and coverage components.

📊 Coverage Collection

Functional coverage metrics tracking FIFO operations, control signals, and edge cases for completeness assessment.

🔄 Reference Model

Behavioral model implementation providing golden reference for scoreboard comparison and expected results generation.

📝 Multiple Test Scenarios

Directed tests (fill, empty) and random stimulus generation for comprehensive and realistic verification coverage.

🔍 FIFO Tracker (NEW)

Advanced transaction tracking with real-time occupancy monitoring, error detection, and detailed statistics reporting.

⚡ Efficient Constraints

Smart constraint distribution with weighted probability for realistic and comprehensive test stimulus generation.

🛠️ Technology Stack

Language

SystemVerilog

IEEE 1800 standard

Methodology

UVM 1.2

Universal Verification Methodology

Simulator

Riviera-PRO

Aldec SystemVerilog Simulator

🏗️ Testbench Architecture

┌─────────────────────────────────────────────────────────┐
│                    TESTBENCH (tb_top)                   │
│  ┌──────────────────────────────────────────────────┐  │
│  │           FIFO Environment                        │  │
│  │  ┌────────────────────────────────────────────┐  │  │
│  │  │        FIFO Agent                          │  │  │
│  │  │  ┌──────────────────────────────────────┐  │  │  │
│  │  │  │  Sequencer  │ Driver  │ Monitor     │  │  │  │
│  │  │  └──────────────────────────────────────┘  │  │  │
│  │  └────────────────────────────────────────────┘  │  │
│  │                        │                          │  │
│  │         ┌──────────────┼──────────────┐          │  │
│  │         ▼              ▼              ▼          │  │
│  │   ┌──────────┐  ┌───────────┐  ┌──────────┐     │  │
│  │   │Coverage  │  │Reference  │  │Scoreboard│     │  │
│  │   │Collector │  │Model      │  │          │     │  │
│  │   └──────────┘  └───────────┘  └──────────┘     │  │
│  │                                                  │  │
│  │                   FIFO Tracker ◄─ Monitor       │  │
│  └──────────────────────────────────────────────────┘  │
│                        │                                │
│                        ▼                                │
│               ┌─────────────────┐                       │
│               │   DUT (FIFO)    │                       │
│               └─────────────────┘                       │
└─────────────────────────────────────────────────────────┘

🔧 Main Components

Sequence Item

Base transaction class with write/read controls and response feedback.

fifo_seq_item.sv

Sequencer & Driver

Manages stimulus generation and applies transactions to DUT via virtual interface.

fifo_sequencer.sv, fifo_driver.sv

Monitor

Captures transactions from DUT on handshake signals. Non-intrusive observation.

fifo_monitor.sv

Agent

Hierarchical container connecting driver, monitor, and sequencer components.

fifo_agent.sv

Reference Model

Behavioral FIFO model generating expected outputs for comparison.

fifo_ref_model.sv

Scoreboard

Compares expected vs. actual results. Reports mismatches and statistics.

fifo_scoreboard.sv

Coverage Collector

Functional coverage tracking for states, operations, and edge cases.

fifo_coverage.sv

⭐ FIFO Tracker

Advanced transaction tracking with occupancy monitoring and statistics.

fifo_tracker.sv (NEW)

📋 Test Scenarios

Directed Tests

Fill Sequence: Fills FIFO to capacity, tests full condition
Empty Sequence: Empties FIFO completely, tests empty condition
Covers boundary conditions and edge cases

Random Testing

Count: 20-200 transactions (configurable)
Distribution: 50% read, 50% write, 80% idle cycles
Comprehensive functional coverage

🔍 FIFO Tracker - Key Capabilities

✓ Real-time Occupancy Tracking - Monitor FIFO size dynamically
✓ Transaction History Logging - Up to 1000 timestamped entries
✓ Error Detection - Write-while-full and read-while-empty

✓ Data Mismatch Detection - Verify data integrity
✓ Comprehensive Statistics - Auto-generated end-of-sim reports
✓ Public Query Methods - Dynamic access to occupancy and counts

📁 Project Files

Design & Testbench
├── design.sv (DUT FIFO implementation)
├── testbench.sv (Top-level testbench)
└── fifo_if.sv (Virtual interface)
UVM Components
├── fifo_pkg.sv (Package)
├── fifo_seq_item.sv (Transaction)
├── fifo_sequence.sv (Stimulus)
├── fifo_sequencer.sv (Sequencer)
├── fifo_driver.sv (Driver)
├── fifo_monitor.sv (Monitor)
├── fifo_agent.sv (Agent)
├── fifo_env.sv (Environment)
└── fifo_test.sv (Test classes)
Verification Components
├── fifo_ref_model.sv (Reference model)
├── fifo_scoreboard.sv (Scoreboard)
├── fifo_coverage.sv (Coverage)
└── fifo_tracker.sv (Transaction tracker) ⭐
Documentation & Scripts
├── documentation.html (Full documentation)
└── run.sh (Simulation script)

⚙️ Quick Start

1. Compile the design and testbench:

vlib work
vlog -timescale 1ns/1ps design.sv testbench.sv

2. Run the simulation:

vsim -c tb_top -do "run -all; quit"

3. Run different test scenarios:

# Directed test (fill/empty)
vsim tb_top +UVM_TESTNAME=fifo_directed_test

# Random test
vsim tb_top +UVM_TESTNAME=fifo_rand_test

1000+

Lines of SystemVerilog

11