Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM Introduction

Universal Verification Methodology (UVM) is a standardized methodology used for functional verification of digital designs using SystemVerilog.

What is UVM?

UVM (Universal Verification Methodology) is a class-based verification framework built on top of SystemVerilog. It was standardized by Accellera to improve reuse, scalability, and productivity in verification environments.

UVM is commonly used for:

  • CPU verification
  • SoC verification
  • Protocol verification
  • IP-level verification
  • Pre-silicon verification

What can UVM do?

  • Create reusable verification components.
  • Generate constrained-random stimulus.
  • Automate checking using scoreboards.
  • Collect functional coverage.
  • Build scalable testbenches for complex designs.
  • Enable verification reuse across projects.

Why UVM?

  • Industry-standard verification methodology.
  • Encourages reusable and modular environments.
  • Supports large and complex verification projects.
  • Works with major simulators (VCS, Questa, Xcelium).
  • Improves verification productivity and maintainability.

Good to know

UVM is written entirely in SystemVerilog and relies heavily on Object-Oriented Programming concepts such as inheritance, polymorphism, and factory patterns.

Most modern verification environments use UVM as the foundation for building reusable verification components.

UVM Compared to Traditional Testbenches

  • Traditional testbenches are usually directed.
  • UVM supports constrained-random verification.
  • UVM separates stimulus, checking, and coverage.
  • UVM enables reusable verification IP (VIP).