Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

Base UVM Classes

Understanding uvm_object and uvm_component

Why These Two Classes Matter

In UVM, almost everything is built on top of two fundamental base classes:

  • uvm_object
  • uvm_component

If you understand the difference between them, you understand the structure of the entire UVM testbench.

uvm_object

uvm_object is the base class for all lightweight, non-hierarchical objects in UVM.

Key Characteristics
  • Does NOT belong to testbench hierarchy
  • No simulation phases
  • Created using new()
  • Supports factory registration
  • Provides utility methods: copy, compare, print, pack, unpack
Typical Examples
  • Sequence items (transactions)
  • Sequences
  • Configuration objects
Example
class my_transaction extends uvm_sequence_item;

  rand bit [7:0] data;

  `uvm_object_utils(my_transaction)

  function new(string name = "my_transaction");
    super.new(name);
  endfunction

endclass

Notice that we use `uvm_object_utils and the object is created with new().

uvm_component

uvm_component is the base class for all hierarchical testbench components.

Key Characteristics
  • Part of UVM testbench hierarchy
  • Has parent-child relationship
  • Participates in simulation phases
  • Created using create() (factory)
  • Has build_phase, connect_phase, run_phase, etc.
Typical Examples
  • Driver
  • Monitor
  • Agent
  • Environment
  • Test
Example
class my_driver extends uvm_driver #(my_transaction);

  `uvm_component_utils(my_driver)

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction

endclass

Notice that:

  • Constructor requires a parent
  • We use `uvm_component_utils
  • Phases are available

Comparison Table

Feature uvm_object uvm_component
Hierarchy No Yes
Phases No Yes
Constructor new(name) new(name, parent)
Factory Creation Optional Recommended / Standard
Used For Transactions, Sequences Drivers, Monitors, Agents

Conceptual Difference

Think of it like this:

  • uvm_object → Data container (like a packet or message)
  • uvm_component → Structural block of the testbench

Components build the testbench architecture. Objects flow inside the architecture.