Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

Hello UVM

In this example, we run our first UVM simulation. The goal is not verification yet, but understanding how a UVM test starts and runs.

What is Hello UVM?

Hello UVM is the simplest possible UVM test. It does not include a DUT, driver, or monitor. The purpose is to verify that the UVM environment runs correctly and prints a message to the simulator log.

After this example, you will understand:

  • How a UVM test starts
  • What run_test() does
  • How to print messages using uvm_info

Hello UVM Test

This is the smallest UVM test that prints a message during simulation.

▶ Run Hello UVM on EDAPlayground

Or copy the following code into EDA Playground. This is the smallest possible UVM test. Its purpose is simply to verify that UVM is running correctly. 

`include "uvm_macros.svh"
import uvm_pkg::*;

class hello_test extends uvm_test;

  `uvm_component_utils(hello_test)

  function new(string name = "hello_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  task run_phase(uvm_phase phase);
    phase.raise_objection(this);

    `uvm_info("HELLO", "Hello from UVM!", UVM_MEDIUM)

    phase.drop_objection(this);
  endtask

endclass

module tb;

  initial begin
    run_test("hello_test");
  end

endmodule
Expected Result

After clicking Run, you should see a message similar to:

UVM_INFO @ 0: reporter [HELLO] Hello from UVM!
What Just Happened?
  • A UVM test was created.
  • UVM started execution using run_test().
  • The test printed a message to the simulator log.
  • You successfully ran your first UVM simulation.
Next Step: In the next section, we will explain how a UVM test is built and how components form the UVM hierarchy.

Understanding the Code

class hello_test extends uvm_test

Creates a UVM test. Every UVM simulation starts from a test class.

`uvm_component_utils(hello_test)

Registers the class with the UVM factory so it can be created by run_test().

task run_phase(uvm_phase phase)

The run phase is where simulation time advances and verification activity happens.

phase.raise_objection(this)

Prevents the simulation from ending immediately by informing UVM that the test is still running.

`uvm_info

Prints a message to the simulator log. This is commonly used for debugging and status information.

Testbench Module

The testbench module starts the UVM test using run_test().

Expected Output

When the simulation runs, you should see a message similar to this:

This confirms that the UVM test executed successfully.

What’s Next?

In the next lesson, we will learn how UVM executes tests using phases and understand when different parts of the testbench run.

Next: UVM Execution Flow →