Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
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Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM RAL – Access Policies (Part 2)

Understanding how common access types affect desired and mirror values.

Overview

UVM supports 25 different access policies in the configure() function. In this section, we focus on the most commonly used ones and understand how they affect the desired and mirror values.

Remember: Access policy controls only the behavior of the register model, not the RTL hardware.

1. RO – Read Only

Write Operation:
  • Writing to DUT has no effect on desired or mirror.
  • Both variables retain their previous values.
Read Operation:
  • Actual DUT value is read.
  • Both desired and mirror are updated with that value.

Key Point: Writes do not update model values.

2. WO – Write Only

Write Operation:
  • Written value is stored in both desired and mirror.
Read Operation:
  • Read operation generates an error.

Key Point: Writes are allowed, reads are illegal.

3. RW – Read/Write

Write Operation:
  • Written value updates desired and mirror.
Read Operation:
  • DUT value is read.
  • Desired and mirror are updated with read value.

Key Point: Standard register behavior.

4. RC – Read Clear

Write Operation:
  • No effect on desired or mirror.
Read Operation:
  • All bits are cleared in desired and mirror.
  • Does NOT store actual read value.

Key Point: Reading clears the register model.

5. RS – Read Set

Write Operation:
  • No effect on desired or mirror.
Read Operation:
  • All bits are set to 1 in desired and mirror.

Key Point: Reading forces all bits to 1 in model.

6. WC – Write Clear

Write Operation:
  • All bits in desired and mirror are cleared.
  • Actual written value is ignored in model.
Read Operation:
  • Read value from DUT updates desired and mirror.

Key Point: Writing clears model bits.

7. WS – Write Set

Write Operation:
  • All bits are set to 1 in desired and mirror.
Read Operation:
  • DUT value updates desired and mirror normally.

Key Point: Writing forces model bits to 1.

Important Clarification

“No effect on write” means: The write does NOT update desired or mirror values.

“No effect on read” means: The read behaves normally and updates desired and mirror with the value read from DUT.

These two statements have completely different meanings.

Summary
  • RO → Write ignored, read updates model.
  • WO → Write updates model, read illegal.
  • RW → Normal read/write behavior.
  • RC → Read clears model bits.
  • RS → Read sets model bits.
  • WC → Write clears model bits.
  • WS → Write sets model bits.