Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVM Coverage Collector
The component responsible for collecting functional coverage from monitored transactions.
📘 What is a Coverage Collector?
A Coverage Collector is a passive UVM component that:
- Receives transactions from the Monitor
- Defines covergroups
- Samples functional scenarios
- Tracks verification completeness
It measures what has been verified, not whether the DUT is correct.
🏗 Position in UVM Architecture
Sequence → Driver → DUT → Monitor → Coverage Collector
The Monitor reconstructs transactions and sends them through an analysis port to the Coverage Collector.
💻 Coverage Collector Example
class my_coverage extends uvm_component;
`uvm_component_utils(my_coverage)
uvm_analysis_imp #(packet, my_coverage) analysis_export;
packet pkt;
covergroup cg;
coverpoint pkt.addr {
bins low = {[0:15]};
bins mid = {[16:127]};
bins high = {[128:255]};
}
coverpoint pkt.write;
cross pkt.addr, pkt.write;
endgroup
function new(string name, uvm_component parent);
super.new(name, parent);
analysis_export = new("analysis_export", this);
cg = new();
endfunction
function void write(packet t);
pkt = t;
cg.sample();
endfunction
endclass
📊 What is Functional Coverage?
Functional coverage ensures that:
- All important scenarios are exercised
- All protocol states are visited
- Corner cases are tested
- Cross combinations are verified
It answers: Did we test everything?
🔄 Coverage Collector vs Scoreboard
| Feature | Coverage Collector | Scoreboard |
|---|---|---|
| Purpose | Measure coverage | Check correctness |
| Uses Covergroups | Yes | No |
| Reports Errors | No | Yes |
| Passive | Yes | Yes |
🚀 Why Coverage is Critical
- Prevents missing corner cases
- Improves regression quality
- Helps achieve coverage closure
- Required for tape-out readiness