Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM RAL – Flexibility Advantage

Understanding Frontdoor and Backdoor Register Access

Flexibility in Register Access

One of the key advantages of UVM RAL is the flexibility it provides when accessing registers during verification. Depending on the verification goal, registers can be accessed either through valid bus transactions or directly without protocol interaction.

Frontdoor Access

Frontdoor access represents real hardware behavior. The RAL model generates valid bus transactions, and register updates occur only after proper protocol execution.

  • Uses valid bus signals (APB, AXI, AHB, etc.)
  • Verifies protocol correctness
  • Represents real system behavior
  • Preferred for functional verification

ral.reg1.write(status, data, UVM_FRONTDOOR);

Backdoor Access

Backdoor access allows registers to be updated directly inside the DUT without applying valid bus transactions. This is useful for debugging, initialization, or isolating specific logic behavior.

  • No bus transaction required
  • Faster register updates
  • Useful for debug and initialization
  • Does not verify bus protocol

ral.reg1.write(status, data, UVM_BACKDOOR);

Frontdoor vs Backdoor Access

Frontdoor
  • Valid protocol execution
  • Real hardware behavior
  • Slower execution
  • Used for functional verification
Backdoor
  • Direct register update
  • No protocol activity
  • Faster execution
  • Used for debug and setup

Verification Insight

A common verification strategy is to validate register functionality using frontdoor access first, and later use backdoor access to accelerate debugging and complex test scenarios.