Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVM TLM Blocking Peek Port
The uvm_blocking_peek_port allows blocking reads (peek) from a connected export.
📘 Overview
A blocking peek port is used when a component needs to read data from a connected export and waits until the data is available.
- Provides synchronous, blocking read access.
- Typically used in scoreboards, monitors, or drivers for checking or capturing transactions.
- Works with UVM TLM 1.0/2.0 interfaces.
🚀 Why Use Blocking Peek Port
- Simple, blocking transaction access.
- Guarantees data is read before continuing.
- Useful in scoreboards for reference model checks.
- Helps implement transaction-based verification.
💻 Example: Blocking Peek Port Usage
class my_scoreboard extends uvm_component;
uvm_blocking_peek_port#(packet) pkt_port;
function new(string name, uvm_component parent);
super.new(name, parent);
pkt_port = new("pkt_port", this);
endfunction
task run_phase(uvm_phase phase);
packet t;
forever begin
pkt_port.peek(t); // blocking read
`uvm_info("SCOREBOARD", $sformatf("Received: %p", t), UVM_MEDIUM)
end
endtask
endclass
The peek() call blocks until a transaction is available from the connected export.
🔗 Typical Connections
- Export: implemented in producer or driver component
- Port: used in consumer like scoreboard or monitor
- Connection is usually established in environment build_phase
// In environment build_phase
producer.pkt_export.connect(scoreboard.pkt_port);
📝 Notes & Tips
- Blocking peek waits for data; ensure no deadlock occurs.
- Do not use inside run_phase loops without
foreversafeguards. - For non-blocking access, consider
uvm_nonblocking_peek_port.