Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVM RAL Adapter Example – APB Protocol
Implementing a protocol-aware adapter for APB-based register access
Why Do We Need a Protocol-Specific Adapter?
In some systems, registers and memories cannot be accessed directly. Instead, they must follow a bus protocol such as APB, AXI, or others.
In this example, the memory is connected through an APB interface. Therefore, all register read/write operations must follow APB signaling:
- pclk
- presetn
- psel
- penable
- pwrite
- paddr
- pwdata
- prdata
- pready
The adapter translates generic RAL operations into APB transactions.
reg_to_bus() – RAL to APB
This function converts the generic uvm_reg_bus_op structure into an APB transaction.
Steps:
- Create APB transaction object
- Determine operation type (READ or WRITE)
- Copy address
- Copy write data
- Return transaction to driver
Instead of directly controlling psel, penable, and pwrite inside the adapter, we use an enum variable named op.
The driver receives this operation type and generates the correct APB handshake signals.
Driver Responsibility
The adapter only indicates whether the operation is READ or WRITE. The driver performs the full APB sequence:
- Set psel = 1
- Set pwrite = 1 (for write)
- Drive paddr and pwdata
- Next cycle: set penable = 1
- Wait for pready
This keeps the adapter simple and protocol-independent.
bus_to_reg() – APB to RAL
This function converts APB transaction results back into the RAL structure.
- Cast bus item to APB transaction
- Update kind (READ/WRITE)
- Copy address
- Capture read data
- Set status = UVM_IS_OK
Whether the protocol is APB, AXI, or custom, the translation principle remains identical.
Summary
- Adapter converts RAL operations to protocol transactions.
- Enum variable simplifies protocol control.
- Driver generates actual APB handshake signals.
- bus_to_reg updates mirror values.
- Process is identical for AXI or any other protocol.