Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVM Plusargs – Commonly Used in Verification
Plusargs are command-line arguments passed to the simulator at runtime. In UVM (Universal Verification Methodology), plusargs allow dynamic configuration of simulations without modifying or recompiling the testbench.
📌 Why Use Plusargs?
- Control test behavior dynamically
- Select tests without recompilation
- Control verbosity and debug output
- Enable or disable features
- Improve regression automation
🔷 Test Control Plusargs
+UVM_TESTNAME
Selects which UVM test to run.
+UVM_TESTNAME=my_test
+UVM_TIMEOUT
Stops simulation after a specified time.
+UVM_TIMEOUT=100000ns
Useful for detecting deadlocks or stalled simulations.
+UVM_MAX_QUIT_COUNT
Stops simulation after a number of UVM errors.
+UVM_MAX_QUIT_COUNT=10
🔷 Verbosity and Reporting Plusargs
+UVM_VERBOSITY
Controls global verbosity level.
+UVM_VERBOSITY=UVM_HIGH
Common Levels:
- UVM_NONE
- UVM_LOW
- UVM_MEDIUM
- UVM_HIGH
- UVM_FULL
- UVM_DEBUG
+UVM_REPORT_DISABLE_FILE_LINE
Removes file and line information from UVM messages. Useful for cleaner logs during regression comparison.
+UVM_REPORT_DISABLE_FILE_LINE
+UVM_PHASE_TRACE
Prints UVM phase execution flow.
+UVM_PHASE_TRACE
🔷 Randomization and Reproducibility
+ntb_random_seed
Sets simulation random seed.
+ntb_random_seed=12345
+UVM_SEED
Alternative seed control used in some flows.
+UVM_SEED=9876
🔷 Debug and Topology Plusargs
+UVM_CONFIG_DB_TRACE
Prints all config_db set/get activity.
+UVM_CONFIG_DB_TRACE
Extremely useful when debugging configuration propagation issues.
+UVM_OBJECTION_TRACE
Displays objection raise/drop activity.
+UVM_OBJECTION_TRACE
Helps debug simulations that never exit run_phase.
+UVM_COMPONENT_TRACE
Shows component creation hierarchy.
+UVM_COMPONENT_TRACE
🔷 Custom Plusargs (User Defined)
Custom plusargs allow dynamic control of sequences or environment behavior.
int num_txn;
if ($value$plusargs("NUM_TXN=%d", num_txn)) begin
`uvm_info("CFG", $sformatf("NUM_TXN = %0d", num_txn), UVM_LOW)
end
Command Line:
+NUM_TXN=100
💡 Industry Best Practices
- Use plusargs for runtime configuration only
- Do not replace config_db usage entirely
- Keep plusargs documented
- Log all plusargs at simulation start
- Use debug plusargs selectively