Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
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UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM RAL – Understanding Different Types of Registers

Learn how different register structures appear in a DUT and how they are modeled in UVM RAL.

Introduction

In UVM Register Abstraction Layer (RAL), registers are modeled inside the verification environment to represent the memory-mapped registers of the DUT.

Registers can vary in structure: some contain a single field, others contain multiple independent fields, and some include reserved or unused bits. Understanding these variations is essential before implementing them in a register model.

1️⃣ Single-Field Register

A register may consist of only one field. For example, a 32-bit register where the entire register behaves as a single field.

  • Register width: 32 bits
  • No explicit field separation
  • The whole register is treated as one field

Even if fields are not explicitly defined, at least one field always exists — the complete register itself.

2️⃣ Multi-Field Register

Many registers contain multiple logical fields grouped within a single 32-bit register.

Example A – Two Fields
  • Slave Control: Bits [15:0]
  • Slave Data: Bits [31:16]
Example B – Four Fields
  • Enable: Bit [0]
  • Mode: Bits [3:1] (3 bits)
  • Address: Bits [11:4] (8 bits)
  • Data: Bits [31:12] (20 bits)

In such cases, each field has a defined size and bit position. These fields are modeled independently using uvm_reg_field.

3️⃣ Registers with Reserved Bits

Some registers contain unused or reserved bits. These bits are typically allocated for future expansion and may not have functional behavior.

Example Structure
  • Mode: Bit [0]
  • Address: Bits [4:1] (4 bits)
  • Data: Bits [20:5] (16 bits)
  • Reserved: Bits [31:21]

In the register model, reserved fields are usually set to a fixed reset value (often zero) and configured so they do not affect functional verification.

Key Takeaways

  • A register always contains at least one field.
  • Registers may have one or multiple independent fields.
  • Each field has a defined bit position and width.
  • Reserved bits must be handled properly in the RAL model.
Summary

In a DUT, registers commonly appear in three forms: single-field registers, multi-field registers, and registers containing reserved bits. Properly identifying and modeling these structures is the first step toward building an accurate UVM RAL register model.