Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueThird Advantage of UVM RAL: Register Comparison Methods
One of the major advantages of the UVM Register Abstraction Layer (RAL) is the availability of built-in methods that allow comparison between the expected register values and the actual values stored in hardware.
During verification, it is important to ensure that the DUT registers contain the correct data and remain synchronized with the register model. UVM RAL simplifies this process by providing automated comparison and synchronization mechanisms.
Two commonly used methods for this purpose are mirror() and update().
1. Mirror Method
The mirror() method is used to verify that the value stored in hardware matches the mirrored value maintained by the RAL model.
The method performs the following operations:
- Reads the register value from the DUT.
- Compares the read value with the mirrored value.
- Reports an error if a mismatch is detected.
This method is commonly used to confirm that a register contains the expected value after configuration or during status verification.
Basic Example
uvm_status_e status;
// Read hardware and compare with mirrored value
reg1.mirror(status, UVM_CHECK);
When UVM_CHECK is used, UVM automatically compares the hardware
value with the mirrored value and reports an error if they differ.
2. Update Method
The update() method is used to synchronize the hardware register with the value stored in the RAL model.
Instead of always performing a write transaction, the update method first checks whether the register is already up to date.
- If the values match, no write transaction is performed.
- If the register is out of date, UVM automatically performs the write.
This reduces unnecessary bus activity and improves simulation efficiency.
Basic Example
uvm_status_e status;
// Update mirrored value only
reg1.set(32'hABCD1234);
// Write to hardware only if needed
reg1.update(status);
The set() method updates only the mirrored value. The
update() method then checks whether hardware needs to be updated.
Summary
The comparison and synchronization methods provided by UVM RAL help maintain consistency between the register model and the DUT. Methods such as mirror() and update() reduce manual checking, improve reliability, and simplify register verification.
These mechanisms allow verification engineers to focus on functionality instead of writing repetitive comparison logic.