Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM Phases

Learn how UVM executes tests using phases and understand the execution flow of a UVM testbench.

What Are UVM Phases?

UVM uses a phase mechanism to control how a testbench is built and executed. Instead of running everything at once, UVM divides execution into ordered steps called phases.

  • Components are created before connections
  • Connections are done before simulation starts
  • Stimulus starts only when everything is ready
  • Simulation ends cleanly

Why Are Phases Important?

Without phases, components could execute in the wrong order:

  • Driver sending transactions before connections exist
  • Sequencer not ready
  • Monitor not built

UVM phases enforce a strict execution order to prevent these problems.

High-Level UVM Execution Flow

UVM execution can be divided into three major stages: 


1. Build the testbench
2. Connect components
3. Run simulation

These stages are implemented using UVM phases.

Main UVM Phases

Phase Purpose
build_phaseCreate components
connect_phaseConnect ports and exports
end_of_elaboration_phaseFinal configuration
start_of_simulation_phasePrepare simulation
run_phaseExecute stimulus
extract_phaseCollect results
check_phaseVerify correctness
report_phasePrint results

Build Phase

The build phase is where components are created. 


function void build_phase(uvm_phase phase);
  super.build_phase(phase);

  driver = driver_type::type_id::create("driver", this);
endfunction
  • Environment is constructed
  • Agents are created
  • Drivers and monitors are instantiated

No simulation time passes here.

Connect Phase

Components are connected together in this phase. 


function void connect_phase(uvm_phase phase);
  driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
  • Connect TLM ports
  • Connect analysis ports
  • Complete communication paths

Run Phase (Most Important)

The run phase is where simulation time runs. 


task run_phase(uvm_phase phase);
  phase.raise_objection(this);

  #100ns;

  phase.drop_objection(this);
endtask
  • Sequences generate transactions
  • Drivers send stimulus
  • Monitors observe DUT activity

Multiple components run in parallel.

Typical Execution Order


build_phase
connect_phase
end_of_elaboration_phase
start_of_simulation_phase
run_phase
extract_phase
check_phase
report_phase

Common Beginner Mistakes

  • Generating stimulus in build_phase
  • Creating components in run_phase
  • Forgetting objections in run_phase

Next Step in UVMArena

After understanding phases, continue with:

UVM Environment — How Components Are Organized