Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVMArena
Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM ComponentsBuilding a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM TestOther Components
Coverage CollectorExecution Model
UVM Phases ObjectionsCommunication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFOConfiguration
UVM Factory UVM Config DBRuntime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime ControlsAdvanced
Virtual Sequences Virtual SequencerUVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror ValueUVM RAL Register Methods
In the UVM Register Abstraction Layer (RAL), each register maintains two important internal values:
- Desired value – the value that the testbench intends to write to the register.
- Mirrored value – the value that the register model believes currently exists in the DUT.
Different UVM methods allow us to manipulate or retrieve these values, and some methods perform actual transactions with the DUT while others only modify the register model.
Desired Value Methods
The desired value represents the value that the testbench wants the register to have. These methods only operate on the register model and do not interact with the DUT.
- set() – Assigns a new value to the desired register value.
- get() – Retrieves the current desired value.
// Example
reg_model.ctrl_reg.set(32'hA5A5);
value = reg_model.ctrl_reg.get();
These methods update only the register model and do not generate any bus transaction.
Mirror Value Method
The mirrored value represents the value that the register model believes is stored inside the DUT register.
This value is automatically updated whenever a transaction occurs.
- get_mirrored_value() – Returns the mirrored value stored in the register model.
value = reg_model.ctrl_reg.get_mirrored_value();
Front-Door Access Methods
Front-door access means interacting with the DUT through the actual bus interface (for example: APB, AXI, AHB).
When these methods are used, they generate real transactions between the testbench and the DUT. As a result, both the desired and mirror values are updated.
- write() – Writes a value to the register through the bus.
- read() – Reads a value from the register.
- update() – Writes the desired value to the DUT register.
- mirror() – Reads the DUT register and updates the mirrored value.
- predict() – Updates the mirror value based on predicted behavior.
- randomize() – Randomizes register values for verification.
// Front-door write
reg_model.ctrl_reg.write(status, 32'h1234);
// Front-door read
reg_model.ctrl_reg.read(status, value);
Backdoor Access Methods
Backdoor access allows direct access to the DUT register without using the bus interface. This is typically done through HDL paths.
These methods are faster because they bypass the bus protocol.
- peek() – Reads the DUT register directly.
- poke() – Writes directly to the DUT register.
// Backdoor write
reg_model.ctrl_reg.poke(32'h55AA);
// Backdoor read
value = reg_model.ctrl_reg.peek();
Two Categories of Register Methods
UVM register methods can be grouped into two main categories:
1. Model-only Methods
- Operate only on the register model.
- Do not interact with the DUT.
- Examples: set(), get(), get_mirrored_value()
2. Transaction Methods
- Perform real transactions with the DUT.
- Update both desired and mirrored values.
- Examples: write(), read(), update(), mirror(), peek(), poke()
Key Takeaways
- UVM registers maintain desired and mirrored values.
- set() and get() manipulate the desired value.
- get_mirrored_value() retrieves the mirrored register value.
- Front-door methods interact with the DUT through the bus.
- Backdoor methods directly access DUT registers without bus transactions.
- Transactions automatically synchronize desired and mirrored values.