Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM Components

UVM Components are the structural building blocks of a UVM testbench. They define hierarchy, manage simulation phases, and coordinate verification behavior.

1. What is a UVM Component?

A UVM component is a class that extends uvm_component. It represents a structural element in the verification environment and participates in the UVM phase mechanism. 

class my_component extends uvm_component;
  `uvm_component_utils(my_component)

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

endclass

Components form a hierarchical tree inside the testbench.

2. UVM Component Hierarchy

UVM components are arranged in a tree structure. The top-level component is usually the uvm_test. 

uvm_test
 └── env
     ├── agent
     │   ├── driver
     │   ├── monitor
     │   └── sequencer
     └── scoreboard

Each component has:

  • A name
  • A parent
  • A position in the hierarchy

3. Common UVM Components

Component Purpose
uvm_test Top-level test configuration and control
uvm_env Container for agents and scoreboards
uvm_agent Encapsulates driver, monitor, sequencer
uvm_driver Drives transactions to DUT
uvm_monitor Observes DUT signals
uvm_sequencer Controls sequence execution
uvm_scoreboard Checks correctness

4. UVM Phases in Components

All UVM components participate in simulation phases. 

function void build_phase(uvm_phase phase);
  super.build_phase(phase);
endfunction

function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);
endfunction

task run_phase(uvm_phase phase);
  phase.raise_objection(this);
  // stimulus generation
  phase.drop_objection(this);
endtask

The most important phases:

  • build_phase – Create components
  • connect_phase – Connect TLM ports
  • run_phase – Execute test stimulus

5. Component vs Object

Feature uvm_component uvm_object
Hierarchy Yes No
Phases Yes No
Factory Registration `uvm_component_utils `uvm_object_utils

Components define structure. Objects define data.

UVMArena Insight: Mastering UVM components is essential to building scalable, reusable, and competition-ready verification environments.