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UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM RAL – Access Policies (Part 3)

Advanced access types: Combined read/write effects and bit-level write behaviors.

Overview

In this section, we explore advanced access policies that combine write behavior with automatic actions during read, as well as bit-specific write policies such as Write-One-to-Clear and Write-Zero-to-Toggle.

As always, these policies only affect how the desired and mirror values are updated in the UVM register model.

1. WRC – Write, Clear on Read

Write Operation:
  • Written value updates desired and mirror normally.
Read Operation:
  • All bits in desired and mirror are cleared.

Behavior: Normal write, but read clears model values.

2. WRS – Write, Set on Read

Write Operation:
  • Written data updates desired and mirror.
Read Operation:
  • All bits in desired and mirror are set to 1.

Behavior: Normal write, but read forces model bits to 1.

3. WSRC – Set on Write, Clear on Read

Write Operation:
  • All bits are set to 1 in desired and mirror.
  • Actual write data is ignored.
Read Operation:
  • All bits are cleared.

Behavior: Write sets everything, read clears everything.

4. WCRS – Clear on Write, Set on Read

Write Operation:
  • All bits are cleared in desired and mirror.
Read Operation:
  • All bits are set to 1.

Behavior: Write clears everything, read sets everything.

Bit-Level Write Policies

These policies modify individual bits based on the value written. Read operation typically behaves normally unless otherwise specified.

W1C – Write One to Clear
  • Any bit written with ‘1’ is cleared.
  • Bits written with ‘0’ remain unchanged.
  • Read operation updates desired and mirror normally.
W1S – Write One to Set
  • Any bit written with ‘1’ is set.
  • Other bits remain unchanged.
  • Read behaves normally.
W1T – Write One to Toggle
  • Bits written with ‘1’ are toggled (complemented).
  • Bits written with ‘0’ remain unchanged.
  • Read behaves normally.
W0C – Write Zero to Clear
  • Bits written with ‘0’ are cleared.
  • Bits written with ‘1’ remain unchanged.
  • Read behaves normally.
W0S – Write Zero to Set
  • Bits written with ‘0’ are set.
  • Bits written with ‘1’ remain unchanged.
W0T – Write Zero to Toggle
  • Bits written with ‘0’ are toggled.
  • Bits written with ‘1’ remain unchanged.
Example – W1C

If we write 100 using W1C:

  • The bit written as ‘1’ gets cleared.
  • Final desired and mirror become 000.

During read, the model updates normally with DUT value.

Summary
  • WRC / WRS combine normal write with automatic action on read.
  • WSRC / WCRS override both write and read behavior completely.
  • W1C, W1S, W1T operate only on bits written as 1.
  • W0C, W0S, W0T operate only on bits written as 0.
  • Most bit-level policies do not affect read behavior.