UVM Getting Started

Learn how to start using UVM without installing tools by using EDA Playground, an online SystemVerilog simulation environment.

Get Started With UVM

At UVMArena, you can start learning UVM without installing any tools on your computer.

In this tutorial, we will use EDA Playground, an online simulation environment that allows you to write and run SystemVerilog and UVM code directly from your browser.

This allows you to focus on learning verification concepts instead of spending time configuring tools.

What is EDA Playground?

EDA Playground is an online platform designed for learning and experimenting with hardware description languages and verification methodologies.

It supports:

• SystemVerilog
• UVM
• Verilog
• VHDL

EDA Playground provides access to industry simulators through a web interface, allowing users to compile and run simulations without local installation.

Why We Use EDA Playground

UVM environments normally require simulator installation, environment configuration, and license setup. These steps can be difficult for beginners.

EDA Playground removes this complexity and allows you to:

• Write code immediately
• Run simulations instantly
• Share examples easily
• Focus on learning UVM concepts

Industry Tools Used for UVM

In professional verification environments, engineers typically use commercial simulators such as:

• Siemens QuestaSim / Questa
• Synopsys VCS
• Cadence Xcelium

The concepts you learn in UVMArena using EDA Playground are directly transferable to these industry tools.

First Step: Open EDA Playground

Go to the EDA Playground website and create a free account.

Open EDA Playground

After logging in:

1. Select SystemVerilog / UVM
2. Choose a simulator
3. Enable the UVM library
4. Write your code in the editor
5. Click Run

Your First UVM Test

Or copy the following code into EDA Playground. This is the smallest possible UVM test. Its purpose is simply to verify that UVM is running correctly.

`include "uvm_macros.svh"
import uvm_pkg::*;

class hello_test extends uvm_test;

  `uvm_component_utils(hello_test)

  function new(string name = "hello_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  task run_phase(uvm_phase phase);
    phase.raise_objection(this);

    `uvm_info("HELLO", "Hello from UVM!", UVM_MEDIUM)

    phase.drop_objection(this);
  endtask

endclass

module tb;

  initial begin
    run_test("hello_test");
  end

endmodule

Expected Result

After clicking Run, you should see a message similar to:

What Just Happened?

• A UVM test was created.
• UVM started execution using run_test().
• The test printed a message to the simulator log.
• You successfully ran your first UVM simulation.