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UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

UVM RAL – Types of Predictors

Understanding Implicit, Explicit, and Passive Prediction in UVM Register Model

What is a Predictor?

A predictor is a component responsible for sampling DUT responses and updating the register model so that it reflects the current hardware state.

Its main purpose is to keep the mirror and desired values of registers synchronized with the actual DUT behavior.

In UVM RAL, predictors ensure that the register abstraction layer stays consistent with what is happening in hardware.

Why Do We Need a Predictor?

  • DUT may modify registers internally.
  • Read data must update mirror value.
  • Scoreboard comparisons require correct register state.
  • Register model must represent real hardware behavior.

Although predictors are commonly used, in some cases a dedicated predictor component is not mandatory.

Three Types of Predictors

  1. Implicit Prediction
  2. Explicit Prediction
  3. Passive Prediction

Each approach updates the register model differently.

1️⃣ Implicit Prediction (Auto Prediction)

In implicit prediction, no separate predictor component is added to the verification environment.

Instead, we enable auto prediction, and the register model updates itself using the response returned by the driver.

How It Works:
  • Register sequence generates a register transaction.
  • Adapter converts it to a bus transaction.
  • Driver applies stimulus to DUT.
  • Driver sends response back to sequencer.
  • Register model updates mirror and desired values automatically.

No monitor-to-predictor connection is required.

This is the simplest prediction mechanism.

2️⃣ Explicit Prediction

In explicit prediction, a dedicated predictor component is added to the verification environment.

How It Works:
  • Register sequence generates transaction.
  • Adapter converts it to bus transaction.
  • Driver applies stimulus to DUT.
  • Monitor captures DUT response.
  • Monitor sends data via analysis port.
  • Predictor receives data and calls predict().
  • Mirror and desired values are updated.

This method provides better visibility and flexibility.

It is commonly used in professional verification environments.

3️⃣ Passive Prediction

In passive prediction, the register model does not generate transactions.

Instead, bus-level sequences generate stimulus.

How It Works:
  • Bus sequence generates bus transaction.
  • Driver applies stimulus to DUT.
  • Monitor captures response.
  • Predictor receives response.
  • Predictor updates register model using predict().

The register model passively observes system behavior.

This approach is useful when verifying DUT behavior independent of RAL sequences.

Comparison of Predictor Types

Type Separate Predictor Reg Sequence Used Complexity
Implicit No Yes Simple
Explicit Yes Yes Moderate
Passive Yes No (Bus sequences) Advanced

Learning Approach

Since implicit prediction is the simplest, we begin with it to understand register methods such as:

  • set()
  • get()
  • predict()
  • mirror()
  • write()
  • read()
  • get_mirrored_value()
  • reset()

Once fundamentals are clear, we gradually move toward explicit and passive prediction mechanisms.

Summary
  • Predictor keeps register model aligned with DUT state.
  • Implicit prediction uses driver response (auto prediction).
  • Explicit prediction uses a dedicated predictor component.
  • Passive prediction updates model from bus-level activity.
  • Implicit is simplest; explicit and passive provide more flexibility.