Introduction
Introduction
SystemVerilog
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SystemVerilog Interview Questions for CPU Design Verification Engineers

SystemVerilog is the main language used in modern hardware verification. CPU verification engineers must understand object-oriented programming, randomization, assertions, and coverage. Below are commonly asked SystemVerilog interview questions with answers.

1. What is the difference between Verilog and SystemVerilog?

Answer:

  • Verilog is mainly a hardware description language.
  • SystemVerilog extends Verilog with verification features.
  • SystemVerilog adds:
    • Object-Oriented Programming
    • Assertions (SVA)
    • Randomization
    • Interfaces
    • Functional coverage

2. What is a class in SystemVerilog?

Answer: Classes enable Object-Oriented Programming in verification environments.


class packet;

  rand bit [7:0] data;
  rand bit write;

  function new();
  endfunction

endclass

3. What is randomization?

Answer: Randomization automatically generates stimulus values.


class packet;

  rand bit [7:0] addr;
  rand bit [31:0] data;

endclass

packet pkt;

initial begin
  pkt = new();
  pkt.randomize();
end

4. What are constraints?

Answer: Constraints control how random values are generated.


class packet;

  rand bit [7:0] addr;

  constraint addr_range {
      addr inside {[0:15]};
  }

endclass

5. Difference between rand and randc?

Keyword Description
rand Random values may repeat
randc Random cyclic values repeat only after all possibilities are used

6. What is an interface?

Answer: Interfaces group signals together and simplify module connections.


interface cpu_if;

  logic clk;
  logic reset;
  logic [31:0] data;

endinterface

7. What is a virtual interface?

Answer: A virtual interface allows classes to access interface signals.


virtual cpu_if vif;

8. What are SystemVerilog assertions?

Answer: Assertions check that a design follows expected behavior.


property req_grant;

 @(posedge clk)
 req |-> ##1 grant;

endproperty

assert property(req_grant);

9. What is functional coverage?

Answer: Functional coverage measures how much of the design functionality has been tested.


covergroup cg;

  coverpoint opcode;

endgroup

10. Difference between code coverage and functional coverage?

Code Coverage Functional Coverage
Measures RTL execution Measures design scenarios
Automatic User defined

11. What is the difference between blocking and non-blocking assignments?


a = b;   // blocking
a <= b;  // non-blocking
  • Blocking executes sequentially.
  • Non-blocking executes concurrently.

12. What is a mailbox?

Answer: Mailboxes are used for communication between processes.


mailbox mb = new();

mb.put(data);
mb.get(data);

13. What is a semaphore?

Answer: A semaphore controls access to shared resources.


semaphore sem = new(1);

sem.get();
sem.put();

14. What is inheritance?


class child extends parent;

Inheritance allows one class to reuse the functionality of another.

15. What is polymorphism?

Polymorphism allows objects of different classes to be accessed through a base class reference.

16. What is encapsulation?

Encapsulation hides internal details of a class and exposes only necessary functionality.

17. What is a queue?


int q[$];

q.push_back(10);
q.pop_front();

Queues are dynamic data structures used frequently in verification.

18. What is a dynamic array?


int arr[];

arr = new[10];

Dynamic arrays are allocated at runtime.

19. Packed vs unpacked arrays?

Packed Unpacked
Bit-level storage Array of elements
Used in RTL Used in testbench

20. What is a clocking block?


clocking cb @(posedge clk);

 input data;
 output valid;

endclocking

Clocking blocks synchronize testbench signals with the clock.

21. What is fork-join?


fork
  task1();
  task2();
join

Fork-join executes processes in parallel.

22. fork-join vs fork-join_any vs fork-join_none?

Type Behavior
join Waits for all threads
join_any Waits for first thread
join_none Does not wait

23. What is DPI?

DPI (Direct Programming Interface) allows SystemVerilog to call C/C++ functions.

24. What are modports?


modport master (input data, output valid);

Modports control how modules access signals in an interface.

25. Why are assertions important in CPU verification?

Assertions help verify:

  • Pipeline correctness
  • Protocol compliance
  • Cache and memory ordering rules

assert property (@(posedge clk) req |-> ##1 grant);