SystemVerilog Interview Questions for CPU Design Verification Engineers – Part 2

This section continues the SystemVerilog interview preparation for CPU Design Verification Engineers. These questions focus on advanced verification concepts such as constraint solving, randomization control, data structures, process synchronization, and simulation semantics.

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1. What are pre_randomize() and post_randomize()?

Answer: These are callback functions executed automatically before and after randomization.

function void pre_randomize();
  $display("Before randomization");
endfunction

function void post_randomize();
  $display("After randomization");
endfunction

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2. What is inline constraint randomization?

Answer: Inline constraints allow adding temporary constraints during a randomize call.

pkt.randomize() with { addr == 16; };

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3. What happens when randomization fails?

The randomize() function returns 0 if constraints cannot be satisfied.

if(!pkt.randomize())
  $fatal("Randomization failed");

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4. What is a soft constraint?

A soft constraint acts as a default constraint that can be overridden by stronger constraints.

constraint addr_c {
  soft addr == 8;
}

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5. What is the dist operator in constraints?

The dist operator controls the probability distribution of randomized values.

constraint opcode_c {
 opcode dist {0 := 70, 1 := 30};
}

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6. What is a packed struct?

typedef struct packed {
  bit [7:0] opcode;
  bit [23:0] addr;
} instr_t;

Packed structs store fields as contiguous bits and are often used in RTL modeling.

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7. What is a union?

union {
  int i;
  bit [31:0] b;
} data_u;

A union allows different variables to share the same memory.

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8. What is an enum?

typedef enum {IDLE, BUSY, DONE} state_t;

Enums provide symbolic names for states and improve code readability.

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9. What is the typedef keyword?

typedef creates an alias for an existing data type.

typedef logic [31:0] word_t;

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10. What is a parameterized class?

class fifo #(int WIDTH = 32);
  bit [WIDTH-1:0] data;
endclass

Parameterized classes allow reusable verification components.

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11. What is the difference between automatic and static functions?

Automatic	Static
Variables created per call	Variables shared across calls
Supports recursion	No recursion

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12. What is a static variable inside a function?

function int counter();

 static int count = 0;
 count++;
 return count;

endfunction

A static variable retains its value between function calls.

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13. What is a named event?

event done;

-> done;
@(done);

Named events allow synchronization between processes.

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14. What is the difference between wait and @?

wait	@ event
Waits for a condition	Waits for a signal event

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15. What is the purpose of disable fork?

disable fork terminates all child processes created by a fork block.

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16. What is unique case?

unique case(opcode)
  0: add();
  1: sub();
endcase

The unique keyword ensures only one case item matches.

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17. What is priority case?

The priority keyword ensures case statements are evaluated in order.

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18. What is a process handle?

process p;

p = process::self();
p.kill();

Process handles allow control of running simulation threads.

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19. What is $strobe?

$strobe prints values at the end of the simulation time step.

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20. Difference between $display and $write?

$display	$write
Adds newline	No newline

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21. What is randcase?

randcase
  3: a = 1;
  1: a = 0;
endcase

randcase randomly selects a branch based on weights.

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22. What is constraint inheritance?

Child classes inherit constraints from parent classes unless disabled.

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23. What is extern in classes?

The extern keyword declares a method inside the class while defining it outside.

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24. What is random stability?

Random stability ensures the same seed produces the same random sequence, which is critical for debugging simulations.

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25. What is the advantage of using enumerated types in verification?

Enumerated types improve readability, debugging, and waveform analysis because symbolic names are displayed instead of raw numbers.