Introduction
Introduction Get started Hello UVM example UVM Phases Part 1 UVM Phases Part 2 UVM Base Classes UVM Object and Core Methods UVM Components
Building a Testbench
UVM Transaction UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Agent UVM Environment UVM Test
Other Components
Coverage Collector
Execution Model
UVM Phases Objections
Communication
TLM Basics TLM Blocking Put Port TLM Non-Blocking Put Port TLM Blocking Peek Port Analysis Ports TLM FIFO
Configuration
UVM Factory UVM Config DB
Runtime Control
UVM Plusargs Seeds & Reproducibility Verbosity Control Debug Runtime Controls
Advanced
Virtual Sequences Virtual Sequencer
UVM RAL
Intro Abstraction Flexibility Comparison Coverage Minimum Requirements Learning Path Register Types First Implementation Register with 2 Fields Register with Reserved Bits Access Policies Part 1 Access Policies Part 2 Access Policies Part 3 Access Policies Part 4 Memory Modeling Register Block Adapter Introduction Adapter Methods Adapter Example Predictor Types Desired and Mirror Values Register Methods Desired Value Mirror Value

SystemVerilog Interview Questions for CPU Design Verification Engineers – Part 4

This section continues the SystemVerilog interview preparation with advanced and practical topics commonly discussed in CPU design verification interviews. The questions focus on constraint behavior, advanced data types, assertions, simulation control, and debugging techniques used in complex verification environments.

1. What is the difference between == and === in SystemVerilog?

Operator Description
== Logical equality (ignores X and Z values)
=== Case equality (compares X and Z exactly)

2. What is the difference between != and !==?

!= performs logical inequality comparison while ignoring unknown values. !== performs case inequality and treats X and Z as valid values.

3. What is the difference between bit and logic?

bit logic
2-state type (0,1) 4-state type (0,1,X,Z)
Faster simulation More accurate modeling

4. What are associative arrays?


int mem[string];

mem["addr1"] = 10;

Associative arrays use arbitrary index types such as integers or strings.

5. What is the difference between associative arrays and dynamic arrays?

Associative Array Dynamic Array
Indexed by arbitrary values Indexed by integers
Sparse memory storage Contiguous memory

6. What is the foreach loop?


foreach(array[i]) begin
  $display(array[i]);
end

The foreach loop iterates through arrays, queues, and associative arrays.

7. What is the do...while loop?


do begin
  i++;
end while(i < 10);

The loop executes at least once before checking the condition.

8. What is the difference between break and continue?

Keyword Behavior
break Exits the loop
continue Skips current iteration

9. What is the purpose of the return statement?

The return statement exits a function and optionally returns a value. 


function int add(int a, int b);
  return a + b;
endfunction

10. What is a virtual class?


virtual class base;

  virtual function void display();
  endfunction

endclass

Virtual classes cannot be instantiated and are used as base classes.

11. What is a pure virtual function?


virtual class base;

  pure virtual function void run();

endclass

A pure virtual function must be implemented in derived classes.

12. What is method overriding?

Method overriding occurs when a child class provides a different implementation of a parent class method.

13. What is the super keyword?


function new();
  super.new();
endfunction

The super keyword accesses parent class methods or constructors.

14. What is the this keyword?

this refers to the current object instance.

15. What is shallow copy vs deep copy?

Shallow Copy Deep Copy
Copies object reference Copies object data
Objects share data Objects are independent

16. What is a copy constructor?

A copy constructor creates a new object by copying the contents of another object.

17. What is the new() constructor in SystemVerilog?


function new(int addr);
  this.addr = addr;
endfunction

Constructors initialize class objects.

18. What is a static class member?


class counter;

 static int count;

endclass

Static members are shared among all class instances.

19. What is a static method?


static function void show();
  $display("Static method");
endfunction

Static methods belong to the class rather than the object.

20. What is the difference between task and function?

Function Task
Returns a value May not return value
No timing control Allows timing control

21. Can a function call a task?

No. Functions cannot call tasks because tasks may contain timing controls.

22. What is the purpose of the automatic keyword?

The automatic keyword creates a new storage instance for variables each time the task or function is called.

23. What is a recursive function?


function automatic int factorial(int n);
  if(n <= 1) return 1;
  return n * factorial(n-1);
endfunction

Recursive functions call themselves.

24. What is the difference between initial and always blocks?

initial always
Runs once Runs repeatedly

25. Why is SystemVerilog object-oriented programming important for verification?

Object-oriented programming allows reusable, modular, and scalable testbench architectures. Frameworks like UVM rely heavily on OOP concepts such as inheritance, polymorphism, and encapsulation.