Introduction
Introduction
SystemVerilog
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SystemVerilog Interview Questions for CPU Design Verification Engineers – Part 3

This section continues SystemVerilog interview preparation with more advanced topics used in modern verification environments. These questions focus on constraint solving behavior, simulation scheduling, assertion features, and RTL/Testbench interaction that verification engineers must understand.

1. What is the constraint_mode() method?

Answer: It enables or disables a constraint block dynamically.


pkt.addr_constraint.constraint_mode(0);

This disables the constraint named addr_constraint.

2. What is the rand_mode() function?

Answer: It enables or disables randomization of a variable.


pkt.addr.rand_mode(0);

3. What is the solve before constraint?

It controls the order in which variables are solved by the constraint solver.


constraint order_c {
  solve addr before data;
}

4. What is constraint implication?

Constraint implication applies a constraint only when a condition is true.


constraint addr_c {
  write -> addr inside {[0:15]};
}

5. What is the purpose of the dist operator?

The dist operator assigns weights to randomized values.


constraint opcode_c {
 opcode dist {0 := 70, 1 := 30};
}

6. What is the SystemVerilog simulation scheduling order?

The main simulation regions include:

  • Preponed
  • Active
  • Inactive
  • NBA (Non-blocking assignment)
  • Observed
  • Reactive
  • Postponed

7. What is a race condition?

A race condition occurs when two or more processes access the same variable at the same simulation time without a defined ordering.

8. What is a delta cycle?

A delta cycle is a simulation step where time does not advance but events are scheduled and executed.

9. What is the purpose of #0 delay?

A #0 delay schedules execution in the next delta cycle without advancing simulation time.

10. What is a final block?


final begin
  $display("Simulation completed");
end

A final block executes once at the end of simulation.

11. What is the difference between $finish and $stop?

$finish $stop
Terminates simulation Pauses simulation for debugging

12. What are sequences in SystemVerilog Assertions?

Sequences define temporal patterns of signals.


sequence req_ack;
  req ##1 ack;
endsequence

13. What is a property in SVA?

A property defines a rule that must hold during simulation.


property req_ack_prop;
 @(posedge clk) req |-> ##1 ack;
endproperty

14. What is the difference between |-> and |=>?

Operator Description
|-> Overlapping implication
|=> Non-overlapping implication

15. What is $past() in SVA?

$past() returns the value of a signal in the previous clock cycle.

16. What is $stable()?

$stable() checks if a signal has not changed value during the current cycle.

17. What is cover property?

It records whether a property has occurred during simulation. 


cover property(req_ack_prop);

18. What is a checker in SystemVerilog?

Checkers encapsulate assertions and verification logic into reusable modules.

19. What is the difference between assert, assume, and cover?

Type Purpose
assert Checks design correctness
assume Used in formal verification
cover Tracks if behavior occurs

20. What is the purpose of timeunit and timeprecision?


timeunit 1ns;
timeprecision 1ps;

They control simulation time resolution.

21. What is the difference between parameter and localparam?

parameter localparam
Can be overridden Cannot be overridden

22. What does $clog2() do?


localparam ADDR_WIDTH = $clog2(256);

It calculates the ceiling of log base 2, commonly used for address width calculations.

23. What is a generate block?


generate
  for(genvar i=0;i<4;i++) begin
     assign out[i] = in[i];
  end
endgenerate

Generate blocks create hardware structures programmatically.

24. What is the purpose of the program block?

Program blocks were introduced to avoid race conditions between testbench and RTL code.

25. Why is simulation scheduling important for verification engineers?

Understanding scheduling regions helps avoid race conditions, debug testbenches, and correctly implement drivers, monitors, and assertions in complex verification environments.