SystemVerilog Interview Questions for CPU Design Verification Engineers – Part 5

This section continues the SystemVerilog interview preparation with topics frequently discussed in advanced verification interviews. The questions focus on constraint behavior, advanced coverage concepts, assertions, randomization control, and debugging strategies used in complex CPU verification environments.

1. What is a constraint block name used for?

Constraint blocks can be named so they can be individually enabled or disabled during simulation.

constraint addr_range {
  addr inside {[0:31]};
}

2. What is the with clause used for in constraints?

The with clause allows applying a filter condition when performing operations such as randomization or array operations.

pkt.randomize() with { addr < 10; };

3. What is a covergroup option?

Covergroup options control how coverage is collected and reported.

covergroup cg;
  option.per_instance = 1;
endgroup

4. What is the purpose of illegal_bins in functional coverage?

Illegal bins detect values that should never occur and generate an error when hit.

coverpoint opcode {
  illegal_bins invalid = {7};
}

5. What are ignore_bins?

Ignore bins specify values that should not be counted toward coverage metrics.

6. What is cross coverage used for?

Cross coverage measures combinations of multiple coverpoints to ensure interactions between signals are tested.

cross opcode, address;

7. What is a wildcard bin?

Wildcard bins allow pattern matching when defining coverage bins.

bins pattern = {8'b10??_????};

8. What is the purpose of bins in coverage?

Bins divide a range of values into categories so the simulator can track how often each category occurs.

9. What is transition coverage?

Transition coverage measures changes between values across clock cycles.

bins transitions = (1 => 2 => 3);

10. What is an automatic covergroup?

An automatic covergroup creates a separate instance of coverage data for each object.

11. What is the difference between assert property and expect property?

12. What is the purpose of the disable iff clause in assertions?

It disables assertion checking when a condition is true.

assert property (@(posedge clk) disable iff(reset) req |-> ack);

13. What is the difference between strong and weak sequences in SVA?

Strong sequences must complete successfully, while weak sequences may terminate early without causing failure.

14. What is the $rose() system function?

$rose(signal) detects a rising edge of a signal.

15. What is the $fell() function?

$fell(signal) detects a falling edge of a signal.

16. What is $changed()?

$changed(signal) checks if a signal value changed between cycles.

17. What is a bind statement?

Bind statements attach assertions or verification modules to RTL without modifying the design.

bind cpu_core checker_module checker_inst();

18. Why is the bind feature useful in verification?

It allows adding assertions and monitors to RTL modules without editing the design code.

19. What is a clocking event?

Clocking events define the timing reference used in assertions or testbench operations.

20. What is a sequence repetition operator?

req ##[1:3] ack

This specifies that ack must occur between 1 and 3 cycles after req.

21. What is the difference between [*] and [->] repetition?

22. What is the purpose of the first_match operator?

It selects the first valid match of a sequence during assertion evaluation.

23. What is coverage closure?

Coverage closure is the process of reaching the target coverage goals by improving test stimulus and adding new test scenarios.

24. What is a regression test?

Regression testing runs large sets of tests automatically to ensure new changes do not break existing functionality.

25. Why is coverage-driven verification important?

Coverage-driven verification ensures that the testbench exercises all important design scenarios, improving confidence that the design is fully verified.