Introduction
Cache Basics Direct Mapped Cache Direct Mapped Example 1 Direct Mapped Example 2 Direct Mapped Problem 1 Direct Mapped Problem 2 Direct Mapped Problem 3 Direct Mapped Problem 4 Direct Mapped Comparators Direct Mapped Disadvantages Direct Mapped Locality Direct Mapped UVM Example Associative Mapped Cache Associative Mapped Problem 1 Associative Mapped Problem 2 Associative Mapped Problem 3 Associative Mapped Problem 4 Set Associative Mapped Cache Set Associative Mapped Comparators Set Associative Mapped Problem 1 Set Associative Mapped Problem 2 Set Associative Mapped Problem 3 Set Associative Mapped Problem 4 Set Associative Mapped Problem 5 Other Mapping Problem - Example 1 Cache Replacement Algorithms LRU Cache Replacement Algorithm FIFO Cache Replacement Algorithm MRU Cache Replacement Algorithm PLRU Cache Replacement Algorithm Round Robin Cache Replacement Algorithm
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Direct Mapped Cache – Disadvantages

Direct mapping is one of the simplest cache mapping techniques. It is easy to implement and requires minimal hardware. However, it also introduces several disadvantages that can negatively affect cache performance.

1. Capacity Miss

A capacity miss occurs when the cache memory becomes full and a new page needs to be loaded. Since there is no free space available, one of the existing pages must be replaced.

If the CPU later requests the page that was replaced, the cache will experience another miss because that page is no longer stored in the cache.

Capacity Miss = Cache miss caused by limited cache size.
Important Points
  • Occurs because the cache has limited storage capacity.
  • When the cache is full, an existing block must be replaced.
  • If the replaced block is needed again later, a cache miss occurs.

This type of miss is not unique to direct mapping. It can occur in any cache mapping technique because cache memory is always limited.

2. Conflict Miss (Collision Miss)

The most important disadvantage of direct mapping is the conflict miss.

In direct mapping, each memory frame can be mapped to only one specific cache line. This mapping is usually determined using a modulo operation:

Cache Line = Frame Number mod Number of Cache Lines

Because of this rule, multiple memory frames may map to the same cache line.

Example
  • Frame 12 → Line 0
  • Frame 8 → Line 0
  • Frame 4 → Line 0

If the cache already contains the page from frame 12 and the CPU requests frame 8, the page from frame 12 must be replaced even if other cache lines are empty.

Later, if the CPU again requests frame 12, the cache will miss because that page was replaced earlier.

Conflict Miss = Cache miss caused by multiple memory frames mapping to the same cache line.
Key Characteristics
  • Occurs even when there is free space in the cache.
  • Happens because of the strict mapping rule of direct mapping.
  • Multiple frames compete for the same cache line.

Why Conflict Miss Happens

In direct mapping, a memory block cannot be placed in any arbitrary cache line. It must go to the line determined by the mapping function.

Because of this restriction:

  • A block may replace another block even when free lines exist.
  • This unnecessary replacement increases cache misses.

Main Disadvantage of Direct Mapping

The biggest disadvantage of direct mapped cache is the conflict miss.

Conflict misses occur specifically because of the rigid mapping rule used in direct mapping. Other cache organizations such as associative mapping can reduce or eliminate this problem by allowing blocks to be stored in multiple possible locations.

Summary

  • Capacity Miss: occurs when the cache is full and blocks must be replaced.
  • Conflict Miss: occurs when multiple memory blocks map to the same cache line.
  • Conflict misses are the main disadvantage of direct mapping.
  • Other cache organizations are designed to reduce these misses.