1. Logical Address Generation

The CPU first generates a logical address. A logical address consists of two fields:

• Page Number
• Page Offset

Example assumptions:

• Process P1 has 4 pages
• Each page contains 4 bytes

To represent 4 pages we need 2 bits:

Each page has 4 bytes, so the offset also needs 2 bits.

2. Example Logical Address

Assume the CPU requests:

• Page 2
• Byte 1

Binary values:

Logical Address = 10 01

3. Logical Address → Physical Address

The logical address is converted into a physical address using the page table.

• CPU uses the Page Table Base Register
• Finds the entry for the requested page
• The entry contains the frame number

Assume:

• Total frames in RAM = 8
• So frame number requires 3 bits

Page 2 is stored in Frame 5.

Physical Address

Frame Number | Offset
101          | 01

4. Accessing RAM

When accessing RAM, the physical address is interpreted as:

Frame Number + Frame Offset

1. Use frame number to locate the frame.
2. Use offset to locate the exact byte.

5. Cache Memory Organization

Assume cache has 4 lines.

To address 4 cache lines we need 2 bits.

6. Address Format for Cache

When accessing cache memory, the physical address is divided into:

Tag | Line Number | Offset

Example using frame number 101:

Tag = 1
Line Number = 01
Offset = 01

The CPU goes directly to Line 1 in the cache.

7. Why Tag is Needed

Multiple frames can map to the same cache line.

Example mapping:

Because both frames map to the same line, the cache stores a tag to identify which frame is currently stored.

• Tag = 0 → Frame 1
• Tag = 1 → Frame 5

8. Cache Access Process

1. CPU generates logical address.
2. Logical address is converted to physical address.
3. Physical address is split into tag, line number, offset.
4. CPU goes directly to the specified cache line.
5. Compare the stored tag with requested tag.

If tags match → Cache Hit

If tags do not match → Cache Miss → Access RAM