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Direct Mapped Cache – Problem 1

1. Given Information

Cache memory contains 4 lines
Line size = 4 bytes
Tag size = 4 bits
Direct mapping technique is used

The problem asks:

Which RAM frames and bytes are currently present in cache memory?

2. Frames Mapped to Each Cache Line

Tag size = 4 bits.

With 4 bits we can generate:

2⁴ = 16 combinations

This means:

16 frames of RAM map to one cache line

Since cache has 4 lines:

Total Frames in RAM = 4 × 16 = 64

Therefore:

RAM contains 64 frames

3. Physical Address Format

A physical address contains:

Frame Number
Frame Offset

Since RAM has 64 frames:

2⁶ = 64

So the frame number requires 6 bits.

The line size is 4 bytes, therefore:

2² = 4

The offset requires 2 bits.

Tag	Line Number	Offset
4 bits	2 bits	2 bits

4. Splitting Frame Number

The 6-bit frame number is divided into:

Tag → 4 bits
Line Number → 2 bits

Example structure:

Frame Number (6 bits)

Tag | Line
----|-----
4b  | 2b

5. Frames Present in Cache

Using the tag and line values provided in the cache table:

Cache Line	Tag	Frame Number (Binary)	Frame Number (Decimal)
Line 0	0101	010100	20
Line 1	0001	000101	5
Line 2	0101	010110	22
Line 3	1110	111011	59

Therefore the frames currently stored in cache are:

Frame 20
Frame 5
Frame 22
Frame 59

6. Bytes Present in Cache

Each frame contains 4 bytes.

If a frame is stored in cache, then all bytes inside that frame are also in cache.

Frame	Bytes Stored
Frame 20	80, 81, 82, 83
Frame 5	20, 21, 22, 23
Frame 22	88, 89, 90, 91
Frame 59	236, 237, 238, 239

7. Cache Hit vs Cache Miss

When the CPU generates a physical address:

The address is checked in cache memory.
If the requested byte is found → Cache Hit
If the requested byte is not found → Cache Miss

In case of a cache miss, the CPU must access the byte from RAM.

8. Summary

Total frames in RAM = 64
Cache lines = 4
Frames currently in cache = 20, 5, 22, 59
Each frame stores 4 bytes
CPU checks cache first before accessing RAM

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