Direct Mapped Cache Verification using UVM

In this example we verify a Direct Mapped Cache using the Universal Verification Methodology (UVM). The goal is to validate the functional behavior of a cache that maps each memory block to a specific cache line using a modulo mapping function.

The verification environment generates randomized read and write transactions, drives them to the DUT, monitors the outputs, and logs the behavior using standard UVM components.

Verification Architecture

The UVM testbench includes the following components:

• Transaction: Defines cache operations (read/write, address, data).
• Sequence: Generates randomized cache requests.
• Driver: Drives transactions to the cache DUT.
• Monitor: Observes DUT signals and forwards them for checking.
• Scoreboard: Logs and checks cache behavior.
• Agent: Groups sequencer, driver, and monitor.
• Environment: Connects the agent and scoreboard.
• Test: Starts the sequences to verify the cache.

Key Features Verified

• Direct mapping logic (index calculation)
• Cache read hits
• Cache read misses
• Write operations
• Tag comparison
• Cache replacement behavior

Code Example

The following simplified code shows the structure of the verification environment. The full implementation is available in the interactive simulation link below.

`include "uvm_macros.svh"
import uvm_pkg::*;

// Transaction
class cache_tx extends uvm_sequence_item;

  rand bit rd_en;
  rand bit wr_en;
  rand bit [15:0] addr;
  rand bit [7:0]  wdata;

  bit [7:0] rdata;
  bit hit;

  `uvm_object_utils(cache_tx)

  function new(string name="cache_tx");
    super.new(name);
  endfunction

endclass


// Sequence
class cache_sequence extends uvm_sequence #(cache_tx);

  `uvm_object_utils(cache_sequence)

  task body();
    cache_tx tx;

    repeat(20) begin
      tx = cache_tx::type_id::create("tx");
      start_item(tx);
      assert(tx.randomize());
      finish_item(tx);
    end

  endtask

endclass
  

Run the Simulation

You can run the complete UVM verification environment directly on EDA Playground.

Learning Outcomes

• Understand how UVM components interact in a verification environment.
• Learn how to verify cache read/write functionality.
• Observe cache hit and miss behavior through simulation.
• Practice building reusable verification environments using UVM.