Introduction
Cache Basics Direct Mapped Cache Direct Mapped Example 1 Direct Mapped Example 2 Direct Mapped Problem 1 Direct Mapped Problem 2 Direct Mapped Problem 3 Direct Mapped Problem 4 Direct Mapped Comparators Direct Mapped Disadvantages Direct Mapped Locality Direct Mapped UVM Example Associative Mapped Cache Associative Mapped Problem 1 Associative Mapped Problem 2 Associative Mapped Problem 3 Associative Mapped Problem 4 Set Associative Mapped Cache Set Associative Mapped Comparators Set Associative Mapped Problem 1 Set Associative Mapped Problem 2 Set Associative Mapped Problem 3 Set Associative Mapped Problem 4 Set Associative Mapped Problem 5 Other Mapping Problem - Example 1 Cache Replacement Algorithms LRU Cache Replacement Algorithm FIFO Cache Replacement Algorithm MRU Cache Replacement Algorithm PLRU Cache Replacement Algorithm Round Robin Cache Replacement AlgorithmUVMArena
Set-Associative Cache Problem – Example 4 (Finding Cache Size)
This example demonstrates how to determine the cache size when only partial information about the cache and memory system is given. The system uses a 4-way set associative cache.
Given Information
| Parameter | Value |
|---|---|
| Main Memory Size | 227 bytes |
| Tag Size | 10 bits |
| Associativity | 4-way set associative |
| Unknown Values | Number of sets and block size |
Cache Size Formula
The total cache size can be calculated as:
Cache Size = Number of Lines × Line Size
In set-associative caches:
Number of Lines = Number of Sets × Lines per Set
Therefore:
Cache Size = (Number of Sets × Lines per Set) × Line Size
Step 1 – Lines per Set
Since the cache is 4-way set associative:
Lines per Set = 4 = 2^2
Step 2 – Assume Address Fields
A physical address in a cache system is divided into three fields:
| Tag | Set Index | Block Offset |
We know:
- Tag size = 10 bits
- Main memory size = 2^27 bytes
Since the system is byte-addressable, the physical address size is:
Physical Address = 27 bits
Step 3 – Remaining Address Bits
The remaining bits correspond to:
- Set index bits = a
- Block offset bits = b
a + b = 27 - 10
a + b = 17 bits
Step 4 – Express Cache Components
Using the variables:
- Number of sets = 2^a
- Line size = 2^b bytes
- Lines per set = 4 = 2^2
Cache size becomes:
Cache Size = (2^a × 2^2) × 2^b
Cache Size = 2^(a + b + 2)
Step 5 – Substitute Known Value
We previously found:
a + b = 17
Therefore:
Cache Size = 2^(17 + 2)
Cache Size = 2^19 bytes
Final Result
Key Insight
When the number of sets and block size are not given, we can represent them using variables. By using the physical address size and the tag size, we can determine the combined number of bits for the set index and block offset.
This allows us to derive the cache size without knowing the exact values of the set index or block offset individually.
Important Concepts
- Cache Size = Number of Lines × Line Size
- Number of Lines = Number of Sets × Lines per Set
- 4-way associative → 4 lines per set
- Physical Address = log₂(Main Memory Size)
- Tag + Set Index + Offset = Physical Address bits