1. System Assumptions

Consider a larger system to understand the Direct Mapping technique.

• RAM contains 32 frames numbered from 0 – 31.
• Cache memory contains 4 lines numbered from 0 – 3.

In direct mapping, RAM frames are mapped to cache lines in a repeating pattern:

Frame 0 → Line 0
Frame 1 → Line 1
Frame 2 → Line 2
Frame 3 → Line 3
Frame 4 → Line 0
Frame 5 → Line 1
Frame 6 → Line 2
Frame 7 → Line 3
...

This pattern continues for all RAM frames.

2. Finding Cache Line for a Frame

Suppose we want to place Frame 26 into cache.

The line number can be calculated using:

Line Number = Frame Number mod Number of Cache Lines

Example:

26 mod 4 = 2

Therefore:

• Frame 26 → Cache Line 2

3. Frame Number Bit Size

Since RAM has 32 frames:

2⁵ = 32

So the frame number requires 5 bits.

Example: Convert frame 26 to binary

26 = 11010

This is the 5-bit frame number.

4. Line Number and Tag Bits

Cache has 4 lines, so we need:

2 bits → Line Number

The frame number has 5 bits, so:

Frame Number (5 bits) = Tag + Line Number

Example for frame 26:

Frame Number = 11010

Tag = 110
Line = 10

Binary 10 means Line 2.

5. Frames Mapped to Each Cache Line

Total frames in RAM = 32

Total cache lines = 4

32 / 4 = 8

So each cache line can store data from 8 different frames.

Example: Frames mapped to Line 0

0
4
8
12
16
20
24
28

These 8 frames share the same cache line.

6. Tag Storage

The tag field identifies which frame is currently stored in the cache line.

Since 8 frames map to one line:

2³ = 8

We need 3 bits for the tag.

For frame 26:

Frame Number = 11010

Tag = 110
Line = 10

The cache line will store:

• Line Number → 2
• Tag → 110

7. Physical Address Format

The physical address consists of:

• Frame Number
• Offset

Assume each frame contains 16 bytes.

2⁴ = 16

So the offset requires 4 bits.

8. Cache Access Process

1. CPU generates a logical address.
2. Logical address is converted to a physical address.
3. The frame number is divided into tag and line number.
4. The CPU directly goes to the specified cache line.
5. The stored tag is compared with the requested tag.

If tags match → Cache Hit

If tags do not match → Cache Miss → Access RAM

9. Accessing the Exact Byte

If the cache hit occurs:

• The CPU uses the offset to locate the exact byte.
• Example: Offset indicates Byte 2 inside the frame.
• The byte is returned to the CPU for execution.

If it is a cache miss, the CPU accesses RAM using the full frame number and offset.