Direct Mapped Cache – Problem 4

In this problem we determine the cache memory size and the tag directory size for a direct mapped cache. As in previous problems, we assume a byte-addressable system, meaning every byte has a unique address.

---

Given

• RAM Size: 32 GB
• Frame Size: 2¹³ bytes
• Tag Size: 10 bits

First convert the RAM size into powers of two.

32 GB = 2⁵ × 2³⁰ = 2³⁵ bytes

Since the system is byte-addressable, the physical address must contain 35 bits.

---

Step 1 – Address Structure

A direct mapped cache address is divided into three fields:

• Tag
• Line Index
• Offset

From the problem statement:

• Tag = 10 bits
• Frame size = 2¹³ bytes

Since each frame contains 2¹³ bytes, the offset requires:

Now we compute the number of bits used for the line index:

Line Bits = Total Address Bits − Tag Bits − Offset Bits

35 − 10 − 13 = 12 bits

---

Step 2 – Number of Cache Lines

If the line index field has 12 bits, then the number of cache lines is:

2¹² lines

---

Step 3 – Cache Memory Size

Each cache line stores one block. Since the frame size is 2¹³ bytes, each cache line also stores 2¹³ bytes.

Cache Size = Number of Lines × Line Size

2¹² × 2¹³ = 2²⁵ bytes

---

Step 4 – Tag Directory Size

Every cache line stores one tag. Therefore the total tag storage is:

Tag Directory Size = Number of Lines × Tag Bits

2¹² × 10 bits

To convert from bits to bytes we divide by 8:

(2¹² × 10) / 8

2¹² / 2³ = 2⁹

---

Alternative Method

Another way to solve the problem is by analyzing the mapping relationship between RAM frames and cache lines.

First compute the number of frames in RAM:

Number of Frames = RAM Size / Frame Size

2³⁵ / 2¹³ = 2²²

The tag field has 10 bits, meaning:

2¹⁰ frames map to a single cache line

Therefore the number of cache lines is:

2²² / 2¹⁰ = 2¹²

Once we know the number of lines and the line size, the cache size is:

2¹² × 2¹³ = 2²⁵ bytes